FPGA Developer – London Leading Global Quant Trading & Investment Firm

Engineering

Dubai

Sep 29, 2024

40000 EUR - 120000 EUR

Full Time

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Job Overview

Date Posted

Sep 29, 2024
Location

Dubai
Offered Salary

40000 EUR - 120000 EUR / Yearly
Expiration date

Dec 6, 2024
Experience

3 Year
Gender

Not required
Qualification

Bachelors
Career Level

Experienced Professional

Job Description

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Founded by experienced quantitative trades, this is one of the largest firms by trading volume on Indian exchanges with a significant market share on several large global exchanges. They’re looking for talented FPGA developers with a full-stack background to help them architect and build out a hardware platform for low-latency trading.

What They Offer

Competitive base salary
Generous perks, including medical insurance, fully equipped cafeteria, paid gym memberships, office games rooms, monthly social events, and an annual offsite
Truly flat organisational structure, where all employees’ ideas are welcomed & valued
Casual, personal and friendly working environment plus health & wellness programs

Key Responsibilities

In this role the workload is varied, with responsibilities that include:

developing low-latency designs in Verilog/System Verilog
developing test harnesses to verify developed items using self-checking test benches, BFMs, etc.
integrating the developed firmware on the target hardware with other system components and software

The production environment is fast moving with a short feedback loop. If you’re smart, ambitious, hardworking and do your best work in a meritocratic environment, apply for this role now

Skills, Experiences

Must have at least 3 years of industry experience in hardware development
Hands-on digital design and FPGA architecture experience is required
Experience of writing RTL in Verilog/System Verilog or VHDL
Strong problem-solving and debugging skills
BSc in Electronics/Engineering-related subject, or equivalent experience
Experience of one of more of the following: self-checking testbenches, BFMs; developing on large Altera and Xilinx FPGAs; scripting; knowledge of Vivado and Questasim; Linux-based environments